Weld quality indicator

ABSTRACT

Apparatus is disclosed for developing a signal proportional to the total energy supplied to a weldment by the electrodes of an electrical welding machine during the welding cycle. The input signal to the apparatus is the AC voltage signal across the electrodes of the welding machine. The signal is rectified, and time integrated over the duration of the weld cycle. The integrated signal, which is proportional to the total energy delivered to the weldment, is compared to preset high and low reference levels. The result of the comparison indicates whether sufficient energy was supplied to the weldment to make a lasting weld.

United States Patent Inventors George Beckman Utica; Tracy B. Gunderman,Clinton, both of, N.Y. Appl. No. 797,802 Filed Feb. 10, 1969 PatentedJune 1, 1971 Assignee Digirnetrics, Inc.

WELD QUALITY INDICATOR 10 Claims, 2 Drawing Figs.

US. Cl 219/109, 219/1 10 Int. Cl 823k 9/10, 823k 1 1/24 Field of Search219/108, 109, 110

[56] References Cited UNITED STATES PATENTS 3,345,493 10/1967 Guetteletal. 219/110 Primary Examiner Bernard A. Gilheany Assistant Examiner-RoyN. Envall, Jr. An0rney-Sughrue, Rothwell, Mion, Zinn & MacPeak ABSTRACT:Apparatus is disclosed for developing a signal proportional to the totalenergy supplied to a weldment by the electrodes of an electrical weldingmachine during the welding cycle. The input signal to the apparatus isthe AC voltage signal across the electrodes of the welding machine. Thesignal is rectified, and time integrated over the duration of the weldcycle. The integrated signal, which is proportional to the total energydelivered to the weldment, is compared to preset high and low referencelevels. The result of the comparison indicates whether sufficient energywas supplied to the weldment to make a lasting weld.

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WELD QUALITY INDICATOR BACKGROUND OF THE INVENTION 1. Field of theInvention The invention relates generally to the field of devices formonitoring the total energy supplied to a weldment by a resistancewelding machine, including indicating and feedback control means.

2. Description of the Prior Art In the course of making a series ofspotwelds using an electrical spot welding machine, there are manyvariable factors which can influence the ultimate strength of each weld.Among the factors to be considered are the condition of the weldingmachine electrodes, the electrode pressure, heat transfer rate of theelectrode cooling system, changes in the welding machines input linevoltage; phase shift or heating of the thyratrons used to supply energyto the weld,'and characteristics of the material being welded, such asits thickness or its surface condition. The present invention providesapparatus which takes into account all of the characteristics of theweld machine and the material being welded in providing an indication ofthe strength of the weld. Previously, the most common method ofdetermining the strength of the spotwelds has been to make a number ofdestructive tests of some of the series of spotwelds, and based on thesetests to make a statistical projection of the probable strength of theaverage weld in the series. But this method is slow, requiring frequentproduction stoppages, and expensive. It also will not detect theoccasional bad weld which will occur in almost any series. The presentinvention provides apparatus for a nondestructive method of determiningthe strength of spotwelds. The invention further provides for testingevery spotweld in the series, rather than just a few welds chosen atrandom.

Prior art weld monitor devices have sought to provide a means fortesting the strength of every weld in a series by measuring the currentapplied to the weld, and comparing the instantaneous magnitude of thiscurrent to preset limits. But the instantaneous magnitude of thiscurrent does not provide sufficient information about a process whereinthe weld strength depends on the total energy supplied over a period oftime. The invention provides means for determining the total energyapplied to the weld and utilizing this to judge weld strength.

Other prior art weld monitoring devices have sought to determine weldstrength by taking the time integral of the current or voltage asmeasured in the welding circuits. But, most of the prior art devices didnot take their input directly across the welding electrodes, which isthe only point at which a truly accurate measurement of the variablesaffecting weld strength can be made. Nor did any of these prior artdevices provide the accuracy and ease of use provided by the presentinvention.

SUMMARY OF THE INVENTION The invention may be broadly summarized asbeing directed to a weld monitoring device which accurately determinesthe total energy delivered during the welding cycle to a spotweld by astandard electrical welding machine. The input voltage signal to themonitoring device is the voltage drop across the welding electrodes ofthe machine. The signal is conditioned to eliminate common modedistortion, and is then applied to a precision rectifier which convertsa previously bipolar signal to a unipolar signal.

The unipolar voltage signal is then applied to an integrator which takesthe integral of the voltage over the time required to complete thewelding cycle. The integrator is controlled by gating signals derivedfrom the voltage signal measured across the electrodes as it is appliedto the weldment to be made. The gating signals control the Integrate,Hold, and Reset modes of the integrator. The magnitude of the resultingvoltage signal which is the integrator output is a function of both thetime required to make the weld and the electrical phenomena occuringwithin the weld. The integrator output voltage is compared topredetermined upper and lower reference levels, and audible and visualindication is given of the results of the comparison. The integratoroutput voltage is also used as the process control variable in afeedback loop to the welding machine. The weld cycle is continued untilthe output voltage exceeds the predetermined lower limit.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a schematic diagram of thecircuitry necessary to take the time integral of the voltage appearingacross the welding machine electrodes.

FIG. 1B is a block diagram of logic circuitry used to control the modesof the integrator and to indicate a pass or fail result for each weldtested.

DETAILED DESCRIPTION OF THE DRAWINGS Referring to FIG. 1A, apparatus isshown for taking the time integral of the voltage drop across theelectrodes 1, 2 of a conventional electric resistance type of spotwelding machine over the time period of the welding cycle. The timeintegral of the voltage is proportional to the total energy delivered toa weldment 3 over the welding cycle. The schematic diagram of FIG. 1Ashows a signal conditioner 10, a rectifier 20, an integrator 30, and ameter 50.

Signal conditioner 10 comprises buffer amplifier A2 and its associatedinput resistance network. Input leads 6, 7 apply the voltage drop acrossthe electrodes of the welding machine (not shown) to the bufferamplifier A2, which is a differential amplifier of conventional design,through a balanced resistive network in which the sum of R4 plus R5 isexactly equal to the sum of R6+R7+R$, where R8 is adjustable to correctfor any imbalance of the resistors. Thus, equal gain is applied to theinput signals on lines 6 and 7, and the amplifier output 8 is a voltagesignal which has positive and negative swings of equal magnitude, andwhich is free of all common-mode distortion. Resistors R1, R2, and R3are used to guarantee a matched low impedance input line. When thewelding electrodes are open, the buffer amplifier inputs are pulled downto ground through these resistors. The combination C7, R9 is astabilization network.

The voltage signal output from signal conditioner 10 is applied to aprecision rectifier 20, which comprises operational amplifiers A1, A3and the associated resistors and diodes, as will be explained more fullybelow.

The first half of this precision rectifier is a conventional operationalamplifier A3; a signal applied to the negative input 9 of this amplifierhas an applied gain of exactly one as determined by resistors R10, R11and R12. Positive input 11 of amplifier A3 is returned to ground througha resistor R14 which for greater precision is equal to the inputresistance to input 9. Amplifier A3 as a stabilization network C2, R13.Amplifier A1, the second half of this precision rectifier, also is aconventional operational amplifier having a gain of one as determined byR21 and R22, R23 and R24. Resistor R22 is a precision adjustmentresistor which is set so thatthe input signal labeled buffer producesexactly twice as much current into node 28 as the signal labeledrectifier for reasons which will be explained below. Positive input 22is returned to ground through resistor R25 which is equal to the inputresistance to negative input 18.

The feedback loop of amplifier A3 has two diodes, CR1 and CR2, inreverse of each other. Thus, the only time the signal rectifier goespositive is when the amplifier output is positive and the amplifierinput 9 is negative. When the amplifier output goes negative, thepotential measured at pin 16 is at.

the signal labeled "buffer" which is a full-wave signal whose magnitudeis equal to the magnitude of the rectifier signal.

As was pointed out above the buffer" signal encounters exactly twice asmuch resistance, into node 28 as does the rectifier signal, R21 and R22,being twice as great as R23. Thus, the rectifier signal produces exactlytwice as much current as the buffer signal into node 28. Also, therectifier signal is I80" out of phase with the buffer signal, since theoutput of amplifi- 3 er' A3 is inverted from its input. Thus, at node28, when the buffer signal is going positive, the rectifier signal is atground; when the 'buffer signal is going negative, the rectifier signalis going positive with a magnitude twice that of the buffer signal. Theresult is that the input to amplifier A2 is a full-wave rectified signaland the output 31 is a signal labeled full-wave, inverted from theinput. The full-wave signal is applied to a gain-controllingpotentiometer 33 and then to integrator 30.

Integrator 30 takes the integral of the input full-wave signal as itappears across potentiometer 33 over the total time that energy issupplied to the weldment. Amplifier A4 is a conventional operationalamplifier having the full-wave signal applied to input 51 through fieldeffect transistor switch 01, and having its other input returned toground through resistor R41.

Amplifier A4 has a high input impedance so that it cannot dischargeintegrating capacitor C1. The charge on the capacitor is registeredthrough current limiting resistor 44 on meter 50.

Meter 50 is a standard milliammeter having display face 54 and meterphotodiodes 68 and 61 illuminated by light source 62. Meter photodiodes68, 61 are positioned on the face of meter 54 to establish theacceptable high and low reference levels respectively of input currentto the meter, and thus the acceptable limits of the charge on capacitorC1. The photodiodes operate in the following manner. As long as thephotodiodes (which is set up directly on the face of the meter) isilluminated by the light source, the diode output voltage signal isconstant. If the illumination is interrupted by the meter needle (notshown) passing between the light source and the diode, the level of thediode output voltage signal changes. In this specific embodiment; thediode output signals are applied to conventional level translators 60,64. The level translators generate binary output signals which change instate in response to a change in input signal level. Thus, if the outputof translator 60 is normally high, a change in the level of theassociated diode output signal, caused by interruption of itsillumination, will result in a change of the translator output signal toa low level. In this manner, the level translators 60, 64 respond to theoutput signals of meter photodiodes 68, 61 to generate binary outputsignals indicating low failure, pass, or high failure. The translatoroutput signals are used to control logic devices in a manner moreparticularly shown and described in FIG. 13.

Field effect switching transistor 02 is used to discharge capacitor C1at the end of a welding cycle. Resistors R43, R49, R48, and R40 act asbiasing and current limiting resistors for transitor switches Q1 and Q2.Diodes CR3 and CR4 are to prevent switching of these transistor switchesby spurious signals.

Integrator 30 operates in one of three modes, Integrate, Hold, or Reset,with the modes controlled by transistor switches Q1 and 02. When theintegrator is in the Integrate mode, switch 01 is closed and switch 02is open, and capacitor C1, responsive to the full-wave signal nowapplied, takes on a charge which is a function of the magnitude of thevoltage drop across electrodes 1, 2 and the time period for which thisvoltage is applied to the weldment. The capacitor charge is proportionalto the total energy supplied to the weldment, and controls thedeflection of the needle on face 54 of milliammeter 50. At the end of aperiod of time which shall be called weld cycle or time period TI,switch 01 opens, switch Q2 remains open and the integrator switches tothe Hold mode. The integrator is now integrating a zero input so thedeflection of the meter needle remains constant, allowing time for anaccurate reading of the meter to be taken. The combined time for theIntegrate and Hold modes is time period T,. At the end of the timeperiod T switch Q2 closes, while switch ()1 remains open, dischargingC1. The integrator is now is the Reset mode, which prepares theintegrator for the next weld cycle. The states of transistor switches 01and 02 are controlled by conventional level translators 1l0 and 120respectively. The level translators have as their inputs binary signalsgenerated by logic devices to be described more particularly inconnection with FIG. 1B. The outputs of the translators are analogsignals which serve to bias transitor switches 01 and 02 into their openand closed states, thus controlling the modes of integrator 30 inresponse to the binary signals.

The logic circuitry which determines whether the charge on capacitor C1(and therefore, the energy applied to weldment 3) is within presetlimits will now be explained in connection with FIG. 1B. The result ofthe determination is expressed by an illumination of the pass lamp 102if the charge is within the limits. If the charge is outside the limits,an illumination of the Fail High lamp 106 or the Fail Low lamp 104indicates which type of failure occurred. In the event of a failure, analarm 108 is also triggered In the block diagram of the logic circuitry,all the logic gates which appear on the drawings are NAND gates; theoutput of a NAND gate is a high level for all conditions except thecondition in which both inputs are high, in which case the output is adown level. The logic circuitry also makes use of four flip-flops 80,90, I30 and 140, each of which consists of a pairs of NAND gates whichare cross-coupled in a manner well known in the art to produce outputsignal which are flipped in response to set and reset input signals.

The full-wave rectifier output signal is picked off rectifier output 31(FIG. 1A) and applied as the input to a conventional level translator70. The level translator translates an analog input into a binaryhigh-down output which can be used to control logic gates of the logiccircuitry. The level translator herein senses the start of the full-wavesignal and in response thereto generates a down-level output T START online 94. The output is applied to starting pulse one-shot 190 whichgenerates a start pulse, which is down-level pulse of short duration, toset flip-flops 80, 190, 130 drawings 140 to their proper initial state.The start pulse is generated by the combination conditions except gates91 and 93 and the are delay RC combination of resistor R60 is capacitorC63. Prior to the start of the weld cycle, line 94 is carrying a highlevel to the input pin F of starting one-shot 190. The result is a downlevel at output pin 97, a high level at input pin 95, and a high outputlevel on line 99. When the rectifier full-wave signal generated duringthe weld cycle is applied to level translator 70 a down level is appliedto pin F of single shot 190, instantly changing the output at pin 97 toa high level. Thus, one input to gate 93 is changed to high; the otherinput remains momentarily high despite the down level at pin F becauseof the time delay presented by the RC combination. The result is a downpulse output on line 99 of a duration equal to the time delay. The startpulse sets flip-flops and and resets flip-flops 130 and 140. The startpulse is necessarily of short duration to allow the flip-flops to bereset at the proper times during the welding cycle.

Setting the integrate cycle flip-flop 80 generates a high level on line83, which is applied to the input of conventional level translator 110.The translator controls the state of field effect transistor switch 01by converting the high and down level outputs of flip-flop 80 to theanalog voltages necessary to open and close the switch. The high leveloutput holds the switch Q1 closed, placing the integrator in theIntegrate mode as explained above. At the end of the weld cycle thefull-wave signal at output pin 31 will return to ground. The output oflevel translator 70 on line 92, which is high during the weld cycle,goes to a down level at the end of the cycle. The down level resets theintegrate cycle flip-flop 80, the signal on line 83 is now a down level,and level translator opens switch 01 ending the Integrate cycle.

The start pulse also sets hold cycle flip-flop 90, producing a highlevel on line 87 and a down level on lines 88, 89. The down level isapplied via line 88 to conventional level translator 120 which controlsthe states of transistor switch 02. As

long as the signal level remains down, the switch O2 is held open. Thesame down level is applied to a conventional time delay device having atime delay equal to time period T which was defined above as being equalto the sum of the time periods for the integrate and Hold cycles. At theend of time period T the output of the delay device being coupled to thereset input of the hold cycle flip-flop, the down level resets theflip-flop generating a high level on output line 88 which is applied bylevel translator 120 to close switch Q2 and initiate the Reset mode.

The down-level output of the integrate cycle flip-flop is also appliedvia line 85 to inverter 151 and then to lamp driver transistor 06. Thedriver transistor will turn on any lamp. or the alarm, unless thecircuit path is closed by a down-level input applied to lamp controltransistors Q7, Q3, Q4 and Q5. The apparatus for developing the high anddown levels at the inputs to these control transistors will now bediscussed.

Meter 50, as explained above, indicates the amount of charge on capacityCl, and also contains two meter photodiodes 68, 61. These photodiodesare placed on the face 54 of meter 50 to represent the acceptable highand low limits of the charge on the integrating capacitor. The outputsof these diodes are applied to their respective conventional leveltranslator 60, 64, which develop binary output signals to be appliedthrough the logic circuitry to control transistors 102- 108.

Responsive to the input of the low diode 61, translator 64 applies tolow line 132 a down level to indicate failure and a high level toindicate pass; the switch from down level to high level is made when theneedle on the face of the meter passes between light source 62 and diode61, momentarily changing the current level input to translator 60.Operating in the same manner, the outputs of translator 68 on high line134 are a high level indicating pass and a down-level indicatingfailure.

Considering first the high fail flip-flop, the flip-flop is reset by thestart pulse, applying a high level to output line 136 which, applied toinverter 154, holds the high fail lamp off; also, the high level on line136 in combination with the high level on low fail flip-flop output line142 causes NAND gate 155 to generate a down level to hold the alarm off.in the case of a high failure, the resulting down level sets flip-flop130, generating a down level on line 136; in response to the down level,high levels are generated by NAND gate 155 and inverter 154 turning onthe high fail light and the alarm.

The low fail flip-flop 140 is also reset by the start pulse; theresulting high level on line 142, applied to inverter 152 and gate 155,holds off the low fail light and the alarm. The level translatorconnected to the low diode has a down-level output, indicating failure,during a part of the integrating cycle while integrating capacitor C1 ischarging; however, the down level is only of interest if it continuesafter the end of time period T,, the welding cycle. Therefore, the downlevel is applied to low fail pulse delay 105, which consists ofinverters 144, 145 and gates 143, 146. Gate 146 will only generate adown level, indicating a low failure and setting the low failureflip-flop, in response to high level inputs from both inverters 144 and145. Inverter 145 produces a high level output in response to a lowfailure, or down level, input; and inverter 144 only produces a highlevel in response to a down level from gate 143, which requires highlevel signal inputs from the set output of flip-flop 90 indicating thestart of time period T,, and the reset output of flip-flop 80,indicating the end of period T,. Thus, if the down-level signal outputof low level signal translator 64 continues past the end of T,, thelow-fail flip-flop is set and the low-fail lamp and the alarm are turnedon.

if neither a high nor a low failure is indicated, then the reset outputsof both flip-flops 130 and 140 remain high and are applied to gate 150and inverter 153 to turn on pass lamp 102.

Inverter 170 is used to pick off a signal for a feedback control system.The output signal will remain high until such time as the charge oncapacitor C1 reaches the preset minimum level indicating that anacceptable amount of energy has been applied to the weldment; the signallevel will then go down,

generating a signal to be used to shut down the welder.

While the invention has been particularly shown and described withreference to preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade therein without departing from the spirit and scope of theinvention.

What we claim is:

1. in combination with an electric spotwelding machine having twoelectrodes through which energy is supplied to a weldment during thewelding cycle, a device for monitoring the total energy supplied to theweldment during the weld cycle, said device comprising:

a. means connected to said two electrodes for rectifying the voltageacross said electrodes,

b. gating means connected to said means for rectifying for generating astart and end welding cycle signal,

c. integrating means connected to said rectifying means and said gatingmeans for integrating the output of said rectifying means between saidstart and end signals to develop a signal which is proportional to theenergy supplied by the electrodes between the start and end signals; and

d. indicator means coupled to said integrating means for indicating theintegrated output from said integrating means.

2. A monitoring device as claimed in claim 1 wherein said integratingmeans comprises a capacitive storage means responsive to said rectifyingmeans output and said gating means for storing a charge proportional tothe total energy supplied to the weldment during the weld cycle.

3. A monitoring device as claimed in claim 2 wherein said gating meansfurther comprises a timing means responsive to said start signal forgenerating a reset signal a predetermined time after the occurrence ofsaid start signal, and said integrating means further comprisesswitching means responsive to said start, end, and reset welding cyclesignals for controlling the charge and discharge times of saidcapacitive storage device.

4. A monitoring device as claimed in claim 3 wherein said capacitivestorage means comprises an operational amplifier with a feedbackcapacitor.

5. A monitoring device as claimed in claim 4 wherein said switchingmeans comprises a first transistorized switch connected between saidrectifying means output and said operational amplifier input forconnecting said rectifying means output to said operational amplifierinput in response to said start signal and disconnecting said rectifyingmeans output from said operational amplifier input in response to saidend signal.

6. A monitoring device as claimed in claim 5 wherein said switchingmeans further comprises a second normally open transistorized switch,connected across said feedback capacitor, responsive to said resetsignal for closing and discharging said feedback capacitor.

7. A monitoring device as claimed in claim 6 wherein said indicatingmeans includes display means connected to said integrating means, forcomparing the output of said integrating means with predeterminedreference levels, and generating a failure indication if the integratoroutput is outside said reference levels.

8. A monitoring device as claimed in claim 7 wherein said display meansfurther comprises a meter having a needle and two positionable meterphotodiodes on the face thereof, said photodiodes being positioned toindicate said predetermined reference levels, said needle beingdeflected in proportion to the output of said integrating means, a lightsource positioned to illuminate said photodiodes, and detection meansresponsive to the interruption of the illumination of said photodiodesfor indicating whether the integrating means output is inside or outsidesaid reference levels.

9. A monitoring device as claimed in claim 8 wherein said display meansfurther comprises a plurality of indicator means responsive to saidgating means and said detecting means for giving visual and audibleindication that the output of said-integrating means is inside oroutside said reference levels.

photodiode output indicates that the output of said integrating means iswithin said preestablished reference levels.

1. In combination with an electric spotwelding machine having twoelectrodes through which energy is supplied to a weldment during thewelding cycle, a device for monitoring the total energy supplied to theweldment during the weld cycle, said device comprising: a. meansconnected to said two electrodes for rectifying the voltage across saidelectrodes, b. gating means connected to said means for rectifying forgenerating a start and end welding cycle signal, c. integrating meansconnected to said rectifying means and said gating means for integratingthe output of said rectifying means between said start and end signalsto develop a signal which is proportional to the energy supplied by theelectrodes between the start and end signals; and d. indicator meanscoupled to said integrating means for indicating the integrated outputfrom said integrating means.
 2. A monitoring device as claimEd in claim1 wherein said integrating means comprises a capacitive storage meansresponsive to said rectifying means output and said gating means forstoring a charge proportional to the total energy supplied to theweldment during the weld cycle.
 3. A monitoring device as claimed inclaim 2 wherein said gating means further comprises a timing meansresponsive to said start signal for generating a reset signal apredetermined time after the occurrence of said start signal, and saidintegrating means further comprises switching means responsive to saidstart, end, and reset welding cycle signals for controlling the chargeand discharge times of said capacitive storage device.
 4. A monitoringdevice as claimed in claim 3 wherein said capacitive storage meanscomprises an operational amplifier with a feedback capacitor.
 5. Amonitoring device as claimed in claim 4 wherein said switching meanscomprises a first transistorized switch connected between saidrectifying means output and said operational amplifier input forconnecting said rectifying means output to said operational amplifierinput in response to said start signal and disconnecting said rectifyingmeans output from said operational amplifier input in response to saidend signal.
 6. A monitoring device as claimed in claim 5 wherein saidswitching means further comprises a second normally open transistorizedswitch, connected across said feedback capacitor, responsive to saidreset signal for closing and discharging said feedback capacitor.
 7. Amonitoring device as claimed in claim 6 wherein said indicating meansincludes display means connected to said integrating means, forcomparing the output of said integrating means with predeterminedreference levels, and generating a failure indication if the integratoroutput is outside said reference levels.
 8. A monitoring device asclaimed in claim 7 wherein said display means further comprises a meterhaving a needle and two positionable meter photodiodes on the facethereof, said photodiodes being positioned to indicate saidpredetermined reference levels, said needle being deflected inproportion to the output of said integrating means, a light sourcepositioned to illuminate said photodiodes, and detection meansresponsive to the interruption of the illumination of said photodiodesfor indicating whether the integrating means output is inside or outsidesaid reference levels.
 9. A monitoring device as claimed in claim 8wherein said display means further comprises a plurality of indicatormeans responsive to said gating means and said detecting means forgiving visual and audible indication that the output of said integratingmeans is inside or outside said reference levels.
 10. A monitoringdevice as claimed in claim 9 further comprising means for generating afeedback control signal whereby said welding cycle will be continueduntil said meter photodiode output indicates that the output of saidintegrating means is within said preestablished reference levels.